This invention relates to a semiconductor integrated circuit device, more particularly a semiconductor integrated circuit device including a bipolar transistor and a method of manufacturing the same.
With recent advances in the art of working, the density of integration of semiconductor integrated circuits has been greatly increased. A typical construction of a prior art integrated circuit device is illustrated in FIG. 1. The integrated circuit device 10 shown therein comprises collector, base and emitter regions 12, 13 and 14 sequentially diffused into one surface of a P type silicon semiconductor substrate 11 by well known techniques and collector, base and emitter electrodes 15, 16 and 17, respectively formed on portions of respective regions to form a bipolar transistor. Reference numeral 18 represents an oxide film, and 19 an embedded or buried layer.
As can be noted from FIG. 1, in the bipolar transistor of the type described above the collector, base and emitter electrodes are arranged on the same plane so that in order to electrically isolate from each other these electrodes it is necessary to insulate them by separating them a certain distance. With the present day working accuracy, the spacing between the electrodes is of the order of 2 to 5 .mu.m. However, the spacing between respective electrodes is an important factor that determines the occupation area of the bipolar transistor. As described above, it is difficult to decrease the electrode spacing in view of the working accuracy so that it is difficult to increase the density of integration so long as the respective electrodes are disposed on the same plane. Furthermore, the electrode spacing is related directly to the parastic capacitance at the collector-emitter junction and the PN junctions between respective regions of the transistor, as well as the base resistance, and when the electrode spacing is increased, the parastic capacitance and the base resistance tend to increase. The limit on the electrode spacing presents an important problem in obtaining a high speed integrated circuit. Further, an increase of the space between electrodes requires long interconnection between elements of the integrated circuit and makes it difficult to arrange interconnecting paths.
Further, with this construction, as it is difficult to self-align the openings or windows of the masks for diffusing the emitter region and for producing respective contacts by photoetching technique, it is necessary to use a high working accuracy of the order of 0.3 .mu.m. Formation of respective electrodes and interconnection also requires a high working accuracy of the order of 0.3 .mu.m. The use of a number of steps requiring such a high working accuracy increases the manufacturing cost of the semiconductor integrated circuit devices.